1. Technical Field
This invention relates generally to memory devices, and more particularly, to memory element fabrication and configuration.
2. Background Art
The volume, use and complexity of computers and electronic devices are continually increasing. Computers consistently become more powerful, new and improved electronic devices are continually developed (e.g., digital audio players, video players). Additionally, the growth and use of digital media (e.g., digital audio, video, images, and the like) have further pushed development of these devices. Such growth and development has vastly increased the amount of information desired/required to be stored and maintained for computer and electronic devices.
Generally, information is stored and maintained in one or more of a number of types of storage devices. Storage devices include long term storage mediums such as, for example, hard disk drives, compact disk drives and corresponding media, digital video disk (DVD) drives, and the like. The long term storage mediums typically store larger amounts of information at a lower cost, but are slower than other types of storage devices. Storage devices also include memory devices, which are often, but not always, short term storage mediums. Memory devices tend to be substantially faster than long term storage mediums. Such memory devices include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), double data rate memory (DDR), flash memory, read only memory (ROM), and the like. Memory devices are subdivided into volatile and non-volatile types. Volatile memory devices generally lose their information if they lose power and typically require periodic refresh cycles to maintain their information. Volatile memory devices include, for example, random access memory (RAM), DRAM, SRAM and the like. Non-volatile memory devices maintain their information whether or not power is maintained to the devices. Non-volatile memory devices include, but are not limited to, ROM, programmable read only memory (PROM), erasable programmable read only memory (EPROM), flash memory and the like. Volatile memory devices generally provide faster operation at a lower cost as compared to non-volatile memory devices.
Memory devices generally include arrays of memory cells. Each memory cell can be accessed or “read”, “written”, and “erased” with information. The memory cells maintain information in an “off” or an “on” state, also referred to as “0” and “1”. Typically, a memory device is addressed to retrieve a specified number of byte(s) (e.g., 8 memory cells per byte). For volatile memory devices, the memory cells must be periodically “refreshed” in order to maintain their state. Such memory devices are usually fabricated from semiconductor devices that perform these various functions and are capable of switching and maintaining the two states. The devices are often fabricated with inorganic solid state technology, such as, crystalline silicon devices. A common semiconductor device employed in memory devices is the metal oxide semiconductor field effect transistor (MOSFET).
The use of portable computer and electronic devices has greatly increased demand for non-volatile memory devices. Digital cameras, digital audio players, personal digital assistants, and the like generally seek to employ large capacity non-volatile memory devices (e.g., flash memory, smart media, compact flash, and the like).
Because of the increasing demand for information storage, memory device developers and manufacturers are constantly attempting to increase storage capacity for memory devices (e.g., increase storage per die or chip). A postage-stamp-sized piece of silicon may contain tens of millions of transistors, each transistor as small as a few hundred nanometers. However, silicon-based devices are approaching their fundamental physical size limits. Inorganic solid state devices are generally encumbered with a complex architecture which leads to high cost and a loss of data storage density. The volatile semiconductor memories based on inorganic semiconductor material must constantly be supplied with electric current with a resulting heating and high electric power consumption in order to maintain stored information. Non-volatile semiconductor devices have a reduced data rate and relatively high power consumption and large degree of complexity. Typically, fabrication processes for such cells are also not reliable.
Therefore, there is a need to overcome the aforementioned deficiencies.
FIG. 1 illustrates a type of memory element 30, which includes advantageous characteristics for meeting these needs. The memory element 30 includes an electrode 32, a superionic passive layer 34 on the electrode 32, an active layer 36 on the superionic layer 34, and an electrode 38 on the active layer 36. Initially, assuming that the memory element 30 is unprogrammed, in order to program the memory element 30, a negative voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Vpg (the “programming” electrical potential) is applied across the memory element 30 from a higher to a lower electrical potential in the forward direction of the memory element 30 (see FIG. 2, a plot of memory element current vs. electrical potential applied across the memory element 30). This potential is sufficient to cause copper ions to be attracted from the superionic layer 34 toward the electrode 38 and into the active layer 36 (A), causing the active layer 36 (and the overall memory element 30) to be in a (forward) low-resistance or conductive state. Upon removal of such potential (B), the copper ions drawn into the active layer 36 during the programming step remain therein, so that the active layer 36 (and memory element 30) remain in a conductive or low-resistance state.
FIG. 3 illustrates the read step of the memory element 30 in its programmed (conductive) state. An electrical potential Vr (the “read” electrical potential) is applied across the memory element 30 from a higher to a lower electrical potential in the forward direction of the memory element 30. This electrical potential is sufficient to overcome the threshold voltage Vt of the inherent diode characteristic of the memory element 30, but is less than the electrical potential Vpg applied across the memory element 30 for programming (see above). In this situation, the memory element 30 will readily conduct current, which indicates that the memory element 30 is in its programmed state.
In order to erase the memory element (FIG. 4), a positive voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Ver (the “erase” electrical potential) is applied across the memory element 30 from a higher to a lower electrical potential in the reverse direction of the memory element 30. This potential is sufficient to cause copper ions to be repelled from the active layer 36 toward the electrode 32 and into the superionic layer 34, causing the active layer 36 (and the overall memory element 30) to be in a high-resistance or substantially non-conductive state (see FIG. 5, illustrating application of electrical potential Ver across the memory element 30). This state remains upon removal of such potential from the memory element 30.
FIG. 6 illustrates the read step of the memory element 30 in its erased (substantially non-conductive) state. The electrical potential Vr is again applied across the memory element 30 from a higher to a lower electrical potential in the forward direction of the memory element 30, as described above. With the active layer 34 (and memory element 30) in a high-resistance or substantially non-conductive state, the memory element 30 will not conduct significant current, which indicates that the memory element 30 is in its erased state.
While such a memory element is highly useful, it has been found that over a period of time and under certain conditions, the low-resistance or conductive state of a programmed memory element 30 may be undesirably diminished. That is, under certain conditions, copper ions drawn into the active layer 36 during the programming step, instead of remaining in the active layer 36 in a stable matter to retain the programmed state of the memory element 30, are not so retained therein at a level necessary to provide the desired conductive or low-resistance state. For example, with the memory element 30 being part of an array including many such memory elements, when an erase electrical potential Ver is applied to a selected memory element from higher to lower potential in the reverse direction thereof, typically, other (non-selected) memory elements in the array also have applied thereto an electrical potential from higher to lower potential in the reverse direction thereof. While this electrical potential is not of sufficient magnitude to erase a non-selected programmed memory element, the application of this potential can cause some copper ions to be repelled from the active layer 36 toward the electrode 32 and into the superionic layer 34 of that non-selected memory element. Over repeated applications of such electrical potential, the number of copper ions undesirably moved from the active layer 36 toward the electrode 32 and into the superionic layer 34 can reach a level that undesirably reduces the conductivity of that non-selected memory element from its programmed state. As another example, over a period of time, under the influence of internal electric fields (without application of external electrical potential), copper ions in the active layer of a programmed memory element may drift from the active layer into the passive layer, again undesirably reducing the conductivity of a programmed memory element.
What is needed is an approach wherein a programmed memory element stably retains its conductive, low resistance state in the above conditions.